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Sandia National Laboratories · Albuquerque, NM
About Sandia: Sandia National Laboratories is the nation's premier science and engineering lab for national security and technology innovation, with teams of specialists focused on cutting-edge work in a broad array of areas. Some of the main reasons we love our jobs: Challenging work with amazing impact that contributes to security, peace, and freedom worldwide Extraordinary co-workers Some of the best tools, equipment, and research facilities in the world Career advancement and enrichment opportunities Flexible work arrangements for many positions include 9/80 (work 80 hours every two weeks, with every other Friday off) and 4/10 (work 4 ten-hour days each week) compressed workweeks, part-time work, and telecommuting (a mix of onsite work and working from home) Generous vacation, strong medical and other benefits, competitive 401k, learning opportunities, relocation assistance and amenities aimed at creating a solid work/life balance World-changing technologies. Life-changing careers. Learn more about Sandia at: http://www.sandia.gov These benefits vary by job classification. What Your Job Will Be Like: We are seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. This role focuses on translating system needs into robust, verifiable RTL through tapeout, with close coordination across analog/MEMS/photonics and physical-design partners. On any given day, you may be called on to: Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques. Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, b